Duty cycle refers to the percentage of time that a digital signal, such as a clock signal, exhibits a high state during a full signal cycle or period. In older digital systems that employ relatively low clock speeds, the duty cycle of a reference clock signal is generally not critical to the performance of the system. However, as clock speed increases, the duty cycle of the clock signal may become very important to digital system performance.
When a high speed clock signal clocks a high performance processor, the duty cycle of that clock signal plays an important role in processor performance. For example, the processor may access system memory on both the leading and trailing edges of clock signal pulses. In that case, memory access speed exhibits a direct relationship to the duration of the clock signal pulses. Thus, the duty cycle of the clock pulses directly affects memory access speed.
Processor system designers typically prefer a 50% duty cycle for the reference clock signal that clocks a processor and memory system. However, the optimum duty cycle of the clock signal for maximum system performance varies with particular semiconductor components. Causes for this variation in the optimum duty cycle include semiconductor process variation and variation in the correlation between semiconductor models and the resultant manufactured semiconductor hardware.
To optimize the duty cycle of a clock signal in a particular application, it is important to first be able to measure the duty cycle of that signal. Unfortunately, measuring the duty cycle of a high speed clock signal in a processor or other digital integrated circuit (IC) presents many problems. For example, if an external duty cycle measurement circuit couples to a clock pin of the IC, the logic in the measurement circuit causes duty cycle degradation of the original clock signal. In other words, the external logic of the measurement circuit alters the duty cycle of the original clock signal thus making the measurement of the duty cycle inherently inaccurate.
Another approach to measuring the clock signal of a digital IC is picosecond imaging circuit analysis (PICA) that detects photons of light emitted on the leading and trailing edges of clock pulses to determine their duty cycle. While this type of duty cycle analysis does work, it is very expensive. Moreover, this type of analysis destroys the component under test.
What is needed is a duty cycle measurement method and apparatus that address the problems discussed above.